Frequently Asked Questions: Xilinx uses the first ASIC-level UltraScale programmable architecture

Frequently Asked Questions: Xilinx begins filming with the first 20nm All Programmable device in the first ASIC-class UltraScale programmable architecture

1. What products will Xilinx announce on July 9, 2013?

Xilinx announced two new industry firsts in 20nm, continuing a series of industry innovations at the 28nm process node:

· Xilinx announced that it is sampling the first 20nm device in the semiconductor industry and the first 20nm All Programmable device in the PLD industry.

· Xilinx's new 20nm devices feature the industry's first ASIC-level programmable architecture, the UltraScaleTM architecture.

2. What does Xilinx mean by “leading the generation” in the 28nm process?

For the 28nm process, Xilinx did not simply port traditional FPGAs to new process nodes. Instead, it designed a number of FPGA innovations and pioneered the industry's first commercial All Programmable 3D ICs and SoCs. This generation of device products has been adopted by end users of hundreds of users. Xilinx has been ahead of its competitors for many years in the launch of breakthrough technology and customer promotion, and has benefited from it.

3. What does Xilinx propose to “continue to lead the generation”?

With the introduction of the UltraScale architecture, we will continue to maintain our edge over the years in the 28nm process. By combining TSMC's cutting-edge technology with collaborative optimization with the Vivado® design suite, Xilinx's UltraScale architecture delivers 1.5x to 2x system-level performance and integration.

4. What is the UltraScale architecture?

The UltraScale architecture applies state-of-the-art ASIC technology in a fully programmable architecture that can scale from 20nm planar FETs to 16nm fin FETs and even more advanced technologies, and can scale from single-chip circuits to 3D ICs. The UltraScale architecture not only addresses the limitations of total system throughput expansion and latency, but also directly breaks through the number one system performance bottleneck on the advanced node, the interconnect issue.

5. What are the advantages of the ASIC-class UltraScale architecture for Xilinx FPGAs, 3D ICs, and SoCs?

The architecture has clear advantages in routing, ASIC-like clock distribution, increased CLB logic, control set functionality, and critical path optimization. These enhancements are designed to meet the demands of customers for higher performance in massive data streams, I/O bandwidth, and real-time packet, DSP and image processing. Incorporating the UltraScale architecture innovation with the Vivado Design Suite, more than 90% of device utilization is achieved without sacrificing performance.

The introduction of the first Kintex® and Virtex® UltraScale devices will further extend Xilinx's All Programmable product line.

6. What is the target application for the UltraScale architecture?

FPGAs based on the UltraScale architecture will support next-generation intelligent systems that meet their new high-performance architectural requirements, including:

· 400G OTN with smart packet processing and traffic management

· 4X4 mixed mode LTE and WCDMA radio with smart beamforming

· 4K2K and 8K display with intelligent image enhancement and recognition

· Highest performance system for intelligent surveillance and detection (ISR)

· High-performance computing applications used in data centers

· Other applications listed on the Xilinx website Xilinx.com

7. How does an UltraScale device complement an existing Xilinx portfolio?

The 7 Series and Zynq-7000 All Programmable Series are industry leaders in system performance, energy efficiency and cost efficiency. For many applications, Xilinx 28nm products will be the best solution for customers in the next few years. In order to support the faster and smarter networks and the growing trend of smart vision and smart devices, a number of applications that require massive data streams will emerge, and the performance required will only be achieved through the Xilinx UltraScale architecture.

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