The liquid crystal driving terminal integrates the liquid crystal controller, the microcontroller, etc., and encapsulates the functions of the liquid crystal control and the graphic interface display through software, opens the operation interface for the user, and shields the control details of the liquid crystal display, so that the user is familiar with The interface (such as RS232 interface) can send a predefined command to control the liquid crystal display and develop the graphical interface.
Currently. The existing liquid crystal drive terminal mainly adopts the method of combining the microcontroller with the front and backstage software, and the terminal can only display the picture mode picture. This type of terminal display data is stored in the built-in NANDFlash. In the human-machine interface design process, the data management in NAND Flash is based on the sector as the basic operation unit. The image download requires special software tools to complete, and the interface is added. The logical complexity and operability of the design. Here, a new type of liquid crystal drive terminal is designed by combining the ARM9 microcontroller with the Linux operating system. The terminal manages the data resources in the CF card through the FAT file system, and uses the multi-thread technology to realize the serial port command parsing and the graphical interface display, not only can display data resources such as fonts and pictures, but also can use the design method to call the MiniGUI graph library. Such resources are suitable for human-machine interface design in the fields of industrial measurement and control, smart meters and so on.
2 system composition and working principle
The system mainly consists of ARM9 microcontroller, storage unit, LCD controller, CF card interface and RS422 communication interface. The block diagram of the system is shown in Figure 1. Workflow: After the system is powered on, the ARM9 microcontroller reads and decompresses the Linux kernel and the Ramdisk root file system from the NOR Flash to the SDRAM. After the pressure is completed, the Linux kernel is booted and the root file system is mounted; when the software environment is initialized After the application is started, the serial port command is started. After the application receives the valid serial port command, the graphic interface data is transmitted to the LCD controller through the Fmmebuffer interface.
3 system main hardware module design
3.1 ARM9 microcontroller
The system uses ATMEL's AT91RM9200 as the MCU. The processor is based on the ARM920T core and operates at 180MHz with a performance of up to 200MVVs. The AT91RM9200 includes a high-speed on-chip SRAM work area and a low latency external bus interface (EBI) for off-chip memory and internal memory
Seamless connection to the peripheral configuration. EBI designed dedicated circuits for SmartMedia, ComDact Flash and NAND F1ash connections. The system uses a MT company's 28F128J3 16 MB NOR Flash for storing the Linux kernel and root file system, using two HY57V281620 to form a 32-bit SDRAM interface.
3.2 LCD driver interface
The system uses EPSON's display control device S1D13506 to control the image data display of the LCD. The S1D13506 is compatible with a wide range of CPU buses and supports LCD interfaces up to 16-bit data width. It can display up to 64 K colors in TFTLCD and CRT. It is equipped with a 16-bit memory interface that supports up to 2 MB of EDO-DRAM. In the system, the S1D13506 is connected to the BANK 3 of the AT91RM9200, and the data bus width is 16 bits. Address line A21 is connected to the S1D13506M/R pin for selecting access registers and memory. The AT91RM9200 accesses the S1D13506 memory memory start address to 0x30200000. The start address of the register is 0x30000000. Using GM71V18163 type 2MBDRAM as display storage, AT91RM9200 realizes data storage operation to DRAM by accessing S1D13506 data address space, using 50 MHz active crystal oscillator as DRAM bus clock, 25 MHz active crystal oscillator as LCD pixel clock signal, Support 640x480 60 Hz TFT LCD display, LCD line, field sync signal is internally divided by S1D13506 to 25 MHz pixel clock. The LCD display control hardware interface circuit is shown in Figure 2.
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